14
LTC1968
1968f
100mV to 110mV (+10%) and back (10%), the step
responses are essentially the same as a standard expo-
nential rise and decay between those two levels. In such
cases, the time constant of the decay will be in between
that of the rising edge and falling edge cases of Figure 10.
Therefore, the worst case is the falling edge response as
it goes to zero, and it can be used as a design guide.
Figure11 shows the settling accuracy vs settling time for
a variety of averaging capacitor values. If the capacitor
value previously selected (based on error requirements)
gives an acceptable settling time, your design is done.
But with 220礔, the settling time to even 10% is a full 10
seconds, which is a long time to wait. What can be done
about such a design? If the reason for choosing 220礔 is
to keep the DC error with a 200mHz input less than 0.1%,
the answer is: not much. The settling time to 1% of 20
seconds is just 4 cycles of this extremely low frequency.
Averaging very low frequency signals takes a long time.
However, if the reason for choosing 220礔 is to keep the
peak error with a 10Hz input less than 0.2%, there is
another way to achieve that result with a much improved
settling time.
APPLICATIO S I FOR ATIO
U
U
U
TIME (SEC)
0
0
20
40
60
80
100
120
0.10 0.20 0.30 0.40
1968 F10a
0.50
C
AVE
= 10礔
Figure 10a. LTC1968 Rising Edge with C
AVE
= 10?/SPAN>F
Figure 10b. LTC1968 Falling Edge with C
AVE
= 10?/SPAN>F
Figure 11. Settling Time vs Cap Value, One Cap Averaging
TIME (SEC)
0
0
20
40
60
80
100
120
0.20 0.40 0.60 0.80
1968 F10b
1
C
AVE
= 10礔
SETTLING TIME (SEC)
0.01
0.1
1
10
1
10
0.1
100
1968 F11
C = 0.1礔
C = 0.22礔
C = 0.47礔
C = 1礔
C = 2.2礔
C = 4.7礔
C = 10礔
C = 22礔
C = 47礔
C = 100礔
C = 220礔
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